Product Compliance

USHTS: 8542320002

ECCN: EAR99

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AS4C SDRAM
Alliance Memory AS4C SDRAM is excessive-speed CMOS synchronous DRAM containing 64Mbits, 128Mbits, or 256Mbits. They are internally configured as 4 banks of 1M, 2M, or 4M word x 16 DRAM with a synchronous interface (all indicators are registered at the high quality fringe of the clock sign, CLK). Read and write accesses to the SDRAM are burst oriented, accesses start at a particular vicinity and continue for a programmed variety of places in a programmed series. Accesses begin with the registration of a BankActivate command, that’s then observed through a Read or Write command.